Integrated circuits (ICs or chips) are manufactured or fabricated in a series of stages, including a front-end-of-line (FEOL) stage, middle-of-line (MOL) stage and back-end-of-line (BEOL) stage. The FEOL, MOL and BEOL stages constitute the process flow for fabricating modern chips. Generally, FEOL stage processes include wafer preparation, isolation, well formation, gate patterning, spacer, extension and source/drain implantation, silicide formation and liner formation. The FEOL stage is where elements (e.g., transistors, capacitors, resistors, etc.) are patterned in the semiconductor. The MOL stage is responsible for gate contact (CA) formation. For example, metal interconnects may be deposited during the MOL stage to connect the elements patterned during the FEOL portion.
Metal interconnects (conductors) are typically formed from aluminum (Al), copper (Cu), cobalt (Co), tungsten (W) or ruthenium (Ru). Additive patterning processes have been developed in order to from the metal interconnects during IC fabrication. One such additive patterning process is generally referred to as a damascene process. In a damascene process, the underlying insulating layer (e.g., silicon oxide layer) is patterned with open trenches where the conductor will be formed. A thick coating of metal is deposited to overfill the trenches, and a subsequent process (e.g., chemical-mechanical planarization or CMP) is used to remove the excess metal extending over the top of the insulating layer. In a single-damascene process, a single trench is formed and filled with metal per each damascene stage. However, a dual-damascene process may be used to form and fill a trench and an underlying via at the same time (i.e., in the same damascene stage). Accordingly, the metal remaining after performing the damascene process becomes the patterned conductor.
One or more air gaps may be formed within an insulating (or dielectric) layer of the IC during the fabrication process to reduce capacitive coupling between adjacent interconnects, and to reduce capacitive loading that may affect signal propagation delays.